I don't think there's a good rule of thumb since there are always multiple factors defining maximum ratings, and the manufacturer might rate some things very conservatively due to testing/model limitations or because for business reasons it was not a priority to find out the true limits.

But I'd definitely worry about exceeding internal voltage limits for small low-voltage devices that are often used in LNAs, than I would worry about thermal limitations.

That makes sense! How about if you test some samples at peak power slightly about the requirement, left them on a hot plate, and saw no measurable change in S-parameters or DC current? Would that be a convincing argument?

Thanks

If made with deep-sub-micron CMOS then the first voltage peak would blow the gate oxide. You might get away with it with SiGe. The rule is the deeper the junction the more hit it can take. That's why E.S.D. diodes are NWELL to substrate.

Richard
Thanks for the thoughts! I should have mentioned this, I was thinking of a GaAs pHEMT LNA design.
Steve